The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Traditional multi-level cell (MLC) NAND flash memory devices are prone to variable error rates within each device due to various conditions. For example, the locations of pages and bits within pages stored on the devices differ and thus are subject to different disturbances causing errors. Ways to reduce such variable error rates may include providing write precompensation or storing variable error correction codes (ECC).
However, such an error reduction schemes are insufficient to handle failures in flash devices beyond random bit errors or noise. More specifically, traditional error reduction schemes are insufficient to compensate for entire wordline failure, multiple page failure, charge pump failure, address decoder failure and/or block failure. One way to mitigate page/block failure may be to use redundant array of independent devices (RAID). However, RAID devices often cannot recover the data when there is more than a single page decoding failure. In addition, while storing variable ECC coding for different data sectors may mitigate such errors, the implementation of variable rate ECC coding in flash memory devices is difficult because these devices are configured to have fixed data sector and page sizes.